1. Field of the Invention
The present invention relates to a semiconductor integrated circuit apparatus and, more particularly, to a test circuit of a semiconductor integrated circuit apparatus that uses a scan path.
2. Description of the Related Background Art
The integration degree or integration density of semiconductor integrated circuits has increased remarkably owing to progress in fine working techniques and following such a tendency the integration degree is expected to increase further in the future. With any increase in integration degree (the number of gates), the degree of difficulty in the testing of semiconductor integrated circuit apparatuses increases exponentially. The ease with which testing of a certain apparatus can be carried out is determined by two factors: the ease with which a failure can be detected at each terminal (observability) and the ease with which each terminal can be set to a desired logical value (controllability). In general, the observability and controllability of the deep terminals (portions far from the periphery) of a large scale logical circuit network are very poor.
The scan test method is recognized as one method of testing a semiconductor integrated circuit apparatus. According to the scan test method, register circuits having the shift register function are inserted at proper positions in the logical circuit network and these register circuits are connected by one shift register path. In the test mode, a test pattern signal is serially fed (input) from the outside of the integrated circuit chip and predetermined data is set into each register. Desired logical signals are applied to the logical circuits connected to the data output terminals of those register circuits, thereby operating the logical circuits. The results of the logical operations are fed from the parallel input terminals of the register circuits into the parallel register circuits. They are then serially output to the outside of the chip to be observed, thereby improving the observability and controllability of the deep terminal of the large scale logical circuit network.
The fundamental idea of the scan test method with respect to a level sensitive synchronous circuit is disclosed in Japanese Patent Publication No. 28614/1977.
Here, however, since the circuit to be tested also includes an asynchronous sequential circuit, an explanation of the prior art will now be made with reference to Japanese Patent Public Disclosure No. 74668/1981.
FIG. 1 shows an example of a conventional test circuit utilizing the scan path method to test an asynchronous type sequential circuit. In the diagram, reference numerals 35 and 37 denote combinational circuit blocks; numeral 36 denotes an asynchronous circuit block including a sequential circuit; numerals 8 to 16 denote scan registers (S.R.) provided between the circuit blocks; and numerals 26 to 34 denote data selectors (D.S.), each for selecting and feeding out (outputting) either the output of the corresponding circuit block or the output of the scan register. The output signal of each circuit block is directly connected to the data input terminal D of the scan registers and to the data input terminal D of the data selectors. On the other hand, the output terminal Q of the corresponding scan register is connected to the test data input terminal (TD) of the data selectors.
The test mode selection terminal (MS) 1 is connected to each mode selection terminal (MS) of the scan registers and data selectors. Numeral 2 denotes a scan-in terminal (SI) and numeral 38 denotes a scan-out terminal (SO). The scan-in terminal 2 is connected to the scan-in terminal SI of the scan register 8. The output terminal Q of the scan register 8 is connected to the scan-in terminal (SI) of the scan register 9. In this manner, the output terminal Q of each scan register is sequentially connected to the scan-in terminal (SI) of the next scan register. Thus, a shift register path is formed between the scan-in terminal 2 and the scan-out terminal 38. Numerals 3 to 5 denote ordinary data input terminals and numeral 6 denotes the scan clock input terminal (TS) connected to the clock input terminal T of the scan register.
FIG. 2 shows an example of the scan registers. MS denotes the mode selection terminal; D is the data input terminal; SI is the scan-in terminal; and T is the clock input terminal. On the other hand, reference numeral 51 denotes an inverter gate; numerals 52 and 53 two-input AND gates; numeral 54 a two-input OR gate; 55 an edge trigger D-type flip-flop (hereinafter, referred to as a D-FF); and Q the data output terminal.
FIG. 3 shows an example of the data selector circuits shown in FIG. 1. MS denotes the mode selection terminal; TD the test data input terminal; D the data input terminal; numeral 60 an inverter gate; numeral 61 and 62 two-input AND gates; numeral 63 a two-input OR gate; and Y an output terminal.
The operation will now be explained.
The operation in the ordinary operating mode will be first described. In this case, a high level ("H") signal is applied to the test mode selection terminal 1 (MS) and the scan clock terminal 6 (TS or T) is fixed to the low level ("L"). Thus, the input and output terminals of the corresponding circuit blocks are directly connected through each data selector.
This point will be explained with reference to FIG. 3. When the "H" signal is supplied to the mode selection terminal (MS), the data selector circuit transfers the data from the data input terminal D to the output terminal Y through the AND gate 62 and the OR gate 63. Since the output of the circuit block is directly connected to the data input terminal D of the data selector, the input and output terminals of the corresponding circuit blocks are directly connected.
However, in the testing operation, the scan mode and test mode are sequentially and repeatedly executed in the following manner, thereby testing each circuit block.